D Type Flip Flops

What is a D-Type Flip Flop?

• A D-Type (Data or Delay) flip flop is a fundamental component in sequential digital circuits
• It is a type of bistable circuit, meaning it has two stable states (0 and 1)
• It is used to store the state of 1 bit of data
• It is a synchronous component, meaning it only changes state based on a clock signal (specifically the “edge” of the signal)

Components

• Data Input ($D$): The value (0 or 1) that we want to store
• Clock Input ($CLK$): Controls when the data is stored
• Output ($Q$): The currently stored value
• Inverted Output ($\bar{Q}$): The opposite of $Q$ (sometimes labelled as NOT Q)

D-Type Flip Flop Symbol

Operation (Positive Edge Triggering)

• The D-Type flip flop is positive edge triggered
• This means it only “looks” at the input $D$ at the precise moment the Clock signal changes from Low (0) to High (1) (the rising edge)

1. Rising Edge occurs: The circuit checks the value of input $D$
2. If $D=1$: Output $Q$ becomes 1 (High)
3. If $D=0$: Output $Q$ becomes 0 (Low)
4. Latch: Between clock pulses, the value of $Q$ remains constant (“latched”), effectively remembering the value even if $D$ changes in the meantime

Use Cases

• Register Memory: Used to create registers inside the CPU
• Counters: Used in digital clocks and timers
• Shift Registers: Used for serial-to-parallel conversion
• Data Storage: Fundamental for Static RAM (SRAM)

Examiner Tips and Tricks

You will not be asked to recall the specific arrangement of logic gates that make up a D-type flip flop, as they can be constructed in various ways.

However, it is useful to know they are often built using NAND gates (AND gates with inverted outputs).

Internal Logic Gate Structure

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Worked Example

Question: Draw the output of the Flip Flop on the diagram below

Method:

• The output line $Q$ should mirror the input $D$, BUT it can only change when the clock signal changes from low to high (indicated by the dotted vertical lines)
• Step 1: Assume $Q$ starts at the same state as $D$ (Low/0 in this case)
• Step 2: Draw the line from left to right. Do not change the level of $Q$ until you hit a vertical dotted line

• Step 3: At the first dotted line, check $D$. $D$ is Low, so $Q$ remains Low.
• Step 4: At the second dotted line (rising edge), check $D$. $D$ is now High, so $Q$ becomes High.

• Step 5: $Q$ is now “latched” at High. Even if $D$ changes in between, ignore it.
• Step 6: At the next dotted line, check $D$. $D$ is still High, so $Q$ remains High.

• Step 7: Continue this process until the end of the diagram.